Allwinner A20 (sun7i) SoC features a Dual-Core Cortex-A7 ARM CPU, and a Mali400 MP2 GPU from ARM.
Allwinner A20 can mostly be seen as a low-end or budget version of the A31 because it shares its Cortex-A7 ARM CPU architecture, but at the same time it is also a bit similar to the A10 because it also features aMali400 GPU, and in addition, the A20 is pin-compatible with its predecessor single-core A10, that means it could greatly simplify the product development process and allows faster time to market. Besides, when compared with A10, A20 is superior in its ultra-low power consumption, which will deeply impress Android tablet and set-top box users.
Allwinner Technology has extended its product lineup to cover a dual-core mobile application processor A20 to better meet the Android tablet and set-top box market demand.
A20 CPU architecture consists of dual ARM Cortex-A7 cores to deliver decent computing capability while consuming less power, and integrates the Mali400 MP2 GPU. It also features CedarX multimedia processing unit that is capable of up to 2160p (3840×1080@30fps 4k resolution or 1080p 3D decoding) video decoding, with integrated HDMI 1.4 output support, and H.264 HP (High Profile) in 1080p at 30fps video encoding.
Officially Allwinner only supports Android 4.2 or above on A20 so far. Linux is not mentioned for any of sun6i or sun67 processors, as AllWinner does not appear have Linux SDK, and Alejandro Mery – one of the main developers at sunxi-linux.org – said the community does not have any source for sun6i at the moment. However, code for “sun7i” for Allwinner A20 has been released.
Cortex-A7 is 100% ISA compatible with the Cortex-A15, this includes the new virtualization instructions, integer divide support and 40-bit memory addressing. Any code running on an A15 can run on a Cortex A7, just slower. This is a very important feature as it enables SoC vendors to build chips with both Cortex A7 and Cortex A15 cores, switching between them depending on workload requirements. ARM calls this a big.LITTLE configuration.
Today, Cortex A7 and A15 virtualization support hardware virtualization.
- It is managed by Xen (Presentation of Cortex A7 and A15 capabilities for virtualisation, Xen ARM on xenproject.org, PVH mode on blog.xen.org, Xen ARMv7 with Vritualization Extensions on xenproject.org wiki)
- Some guides to deploy virtualization on Cotex-A15 and source for virtualization with KVM on Cortex-A15 on github
On the kvm branch of kernel.org, there is description of Cortex-A15 Vitrualization extensions VGIC registers :
After the ARM Cortex-A7 documentation:
- GIC memory MAP on Cortex-A7:
0x4000-0x4FFF Virtual interface control, common base address 0x5000-0x5FFF Virtual interface control, processor-specific base address 0x6000-0x7FFF Virtual CPU interface
- Virtual Maintenance Interrupt (PPI6)
- 2 virtual interrupt signals, nVIRQ and nVFIQ
- With MMU-400, Intermediate Physical Address (IPA) ca be used by guest OS
A20 SoC Features
- ARM Cortex-A7 Dual-Core
- 256KiB L2-Cache (shared between two cores)
- 32KiB (Instruction) / 32KiB (Data) L1-Cache per core
- SIMD NEON, VFP4
- Large Physical Address Extensions (LPAE) 1TB
- ARM Mali400 MP2
- Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).
- Complies with OpenGL ES 2.0
- LPDDR2/DDR3/DDR3L controller
- NAND Flash controller and 64-bit ECC
- HD H.264 2160P video decoding
- Full HD video decoding
- BD Directory, BD ISO and BD m2ts video decoding
- H.264 High Profile 1080P@30fps encoding
- 3840×1080@30fps 3D decoding
- Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol
- Support multi-channel HD display
- Integrated HDMI 1.4
- CPU/RGB/LVDS LCD interface 1920×1080 resolution
- CVBS/YPbPr/VGA support
- Integrated TV decoder
- Integrated parallel 8-bit I/F YUV sensor
- Integrated 24-bit parallel YUV 444 I/F
- 5M/8M CMOS sensor support
- Dual-sensor support
- Integrated HI-FI 100dB Audio Codec
- Dual MIC noise cancellation
- ↑ http://olimex.wordpress.com/2013/04/05/allwinners-a10-and-a20-are-they-really-pin-to-pin-compatible-and-drop-in-replacement/ Olimex finds pin (in)compatibilities
- ↑ http://www.cnx-software.com/2012/12/09/allwinner-a31-and-a20-processors-details/ Allwinner Publishes A31 and A20 Processors Details
- ↑ http://www.anandtech.com/show/4991/arms-cortex-a7-bringing-cheaper-dualcore-more-power-efficient-highend-devices
- ↑ http://en.wikipedia.org/wiki/ARM_Cortex-A7_MPCore][http://www.arm.com/products/processors/cortex-a/cortex-a7.php
- ↑ Cortex-A7 MPCore Technical Reference Manual – 8.2.1. GIC memory-map
- ↑ Cortex-A7 MPCore Technical Reference Manual – 8.2.2. Interrupt sources
- ↑ Cortex-A7 MPCore Technical Reference Manual – 8.2.4. GIC configuration
- ↑ CoreLink MMU-400 System Memory Management Unit Technical Reference Manual – 1.1. About the MMU-400
- Product Page
- kernel source code for Allwinner A20
- Allwinner A20 EVB Schematics
- Allwinner A20 product brief
- Allwinner A20 article on wikipedia.org
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